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FPD4000AS
2.5W PACKAGED POWER PHEMT * PERFORMANCE (1.8 GHz) 34.5 dBm Output Power (P1dB) 12 dB Power Gain (G1dB) 45 dBm Output IP3 8V Operation 50% Power-Added Efficiency Evaluation Boards Available Design Data Available on Website Suitable for applications to 5 GHz DESCRIPTION AND APPLICATIONS
SEE PACKAGE OUTLINE FOR MARKING CODE
*
The FPD4000AS is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron Mobility Transistor (pHEMT), optimized for power applications in L-Band. The surface-mount package has been optimized for low parasitics. Typical applications include drivers or output stages in PCS/Cellular base station transmitter amplifiers, as well as other power applications in WLL/WLAN amplifiers. * ELECTRICAL SPECIFICATIONS AT 22C
Parameter Power at 1dB Gain Compression Power Gain at dB Gain Compression Maximum Stable Gain S21/S12 Power-Added Efficiency at 1dB Gain Compression 3 -Order Intermodulation Distortion S and L tuned for Optimum IP3 Saturated Drain-Source Current Maximum Drain-Source Current Transconductance Gate-Source Leakage Current Pinch-Off Voltage Gate-Source Breakdown Voltage Gate-Drain Breakdown Voltage Thermal Resistivity (channel-to-case) IDSS IMAX GM IGSO |VP| |VBDGS| |VBDGD| CC
rd
Symbol P1dB G1dB MSG PAE IM3
Test Conditions VDS = 8V; IDQ = 700 mA S and L tuned for Optimum IP3 VDS = 8V; IDQ = 700 mA S and L tuned for Optimum IP3 VDS = 8V; IDQ = 700 mA PIN = 0dBm, 50 system VDS = 8V; IDQ = 700 mA S and L tuned for Optimum IP3 VDS = 8V; IDQ = 700 mA POUT = 23 dBm (single-tone level) VDS = 1.3 V; VGS = 0 V VDS = 1.3 V; VGS +1 V VDS = 1.3 V; VGS = 0 V VGS = -3 V VDS = 1.3 V; IDS = 8 mA IGS = 8 mA IGD = 8 mA See Note on following page
Min 33.5 10.5
Typ 34.5 12 18 50
Max
Units dBm
RF SPECIFICATIONS MEASURED AT f = 1.8 GHz USING CW SIGNAL
dB %
-46 1.9 2.3 3.6 2.4 70 0.7 6 20 0.9 10 22 16 170 1.4 2.65
dBc mA mA mS A V V V C/W
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 05/26/05 Email: sales@filcsi.com
FPD4000AS
2.5W PACKAGED POWER PHEMT * RECOMMENDED OPERATING BIAS CONDITIONS Drain-Source Voltage: From 5V to 8V Quiescent Current: From 400 mA to 750 mA ABSOLUTE MAXIMUM RATINGS1
Parameter Drain-Source Voltage Gate-Source Voltage Drain-Source Current Gate Current RF Input Power
2
*
Symbol VDS VGS IDS IG PIN TCH TSTG PTOT Comp.
3
Test Conditions -3V < VGS < +0V 0V < VDS < +8V For VDS > 2V Forward / Reverse current Under any acceptable bias state Under any acceptable bias state Non-Operating Storage See De-Rating Note below Under any bias conditions
Min
Max 12 -3 IDSS +20/-20 575 175
Units V V mA mA mW C C W dB %
Channel Operating Temperature Storage Temperature Total Power Dissipation Gain Compression
1
-40
150 9.0 5
Simultaneous Combination of Limits 2 or more Max. Limits 80 2 TAmbient = 22C unless otherwise noted Max. RF Input Limit must be further limited if input VSWR > 2.5:1 3 Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes: * Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device. * Total Power Dissipation defined as: PTOT (PDC + PIN) - POUT, where: PDC: DC Bias Power PIN: RF Input Power POUT: RF Output Power * Total Power Dissipation to be de-rated as follows above 22C: PTOT= 9.0 - (0.0625W/C) x TPACK where TPACK = source tab lead temperature above 22C (coefficient of de-rating formula is the Thermal Conductivity) Example: For a 55C source lead temperature: PTOT = 9.0 - (0.0625 x (55 - 22)) = 6.94W * For optimum heatsinking, metal-filled through (Source) via holes should be used directly below the central metallized ground pad on the bottom of the package. * Note on Thermal Resistivity: The nominal value of 16C/W is measured with the package mounted on a large heatsink with thermal compound to ensure adequate (unsoldered) contact. The package temperature is referred to the Source leads.
*
HANDLING PRECAUTIONS To avoid damage to the devices care should be exercised during handling. Proper Electrostatic Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and testing. This product has be tested to Class 1A (> 250V but < 500V) using JESD22 A114, Human Body Model, and to Class A, (< 200V) using JESD22 A115, Machine Model.
Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 05/26/05 Email: sales@filcsi.com
FPD4000AS
2.5W PACKAGED POWER PHEMT
*
BIASING GUIDELINES Active bias circuits provide good performance stabilization over variations of operating temperature, but require a larger number of components compared to self-bias or dual-biased. Such circuits should include provisions to ensure that Gate bias is applied before Drain bias, otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for additional information. Dual-bias circuits are relatively simple to implement, but will require a regulated negative voltage supply for depletion-mode devices such as the FPD1000AS. Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source bias voltage, and such circuits provide some temperature stabilization for the device. A nominal value for circuit development is 3.25 for the recommended 200mA operating point. The recommended 200mA bias point is nominally a Class AB mode. A small amount of RF gain expansion prior to the onset of compression is normal for this operating point.
*
PACKAGE OUTLINE AND RECOMMENDED PC BOARD LAYOUT (dimensions in millimeters - mm)
PACKAGE MARKING CODE
Example: f1ZD P1F
f = Filtronic 1ZD = Lot / Date Code P1F = Status, Part Code, Part Type
All information and specifications subject to change without notice. Phone: +1 408 850-5790 Fax: +1 408 850-5766
http:// www.filtronic.co.uk/semis
Revised: 05/26/05 Email: sales@filcsi.com

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